1. Field of the Invention
The present invention relates generally to read-only-memories, and, more particularly, to a series read-only-memory which has capacitive bootstrap precharging circuitry.
2. Background Art
In general, read-only-memories (ROM's) are implemented in either NOR/OR logic or NAND/AND logic. In ROM's of the NOR/OR type, the logic states of individual data bits are typically represented by the presence or absence of transistors at selected locations within an array of transistor sites. Upon the selection of one of the word lines, each of the transistors which are present in the corresponding row of the array will be enabled. Since the transistors which are present in each column of the array are connected in parallel to a respective bit line, the enabling of any one of the transistors in a column via one of the word lines will discharge the precharged bit line. Thus, the logic state of the bit "stored" at the junction of the selected word line and a particular one of the bit lines will be reflected by the state of that bit line after the selection of that word line. A typical ROM of the NOR/OR type is shown and described in U.S. Pat. No. 4,350,992.
In ROM's of the NAND/AND type, the logic states of data bits are typically represented by the type of transistor, e.g. enhancement or depletion, which is fabricated at the respective transistor sites. Upon the selection of one of the word lines, every enhancement transistor present in the corresponding row of the array will be disabled, while the depletion transistors, if any, in the row will remain enabled. Since the transistors which are present in each column of the array are connected in series to form a respective bit line, the disabling of any one of the enhancement transistors in a column via one of the word lines will prevent the discharge of the precharged bit line. Thus, the logic state of the bit represented by the transistor at the junction of the selected word line and the particular bit line will be reflected by the state of that bit line after the selection of that word line. An early ROM of the NAND/AND type is described in U.S. Pat. No. 4,059,826.
In general, ROM's of the NAND/AND type are considerably smaller than the comparably sized NOR/OR type because the series-connected transistors can be fabricated without interlayer contacts and without a distributed discharge line. However, the cumulative resistances of the series-connected transistors impede the discharge of the bit lines. Thus, ROM's of the NOR/OR type are typically faster than those of the NAND/AND type because the bit lines can be very rapidly discharged by any one of the parallel-connected transistors.
One ROM of the series type which provided a respectable cycle time is described in "Minimum Size ROM Structure Compatible with Silicon-Gate E/D MOS LSI" on pages 360-364 of the June 1976 issue of IEEE Journal of Solid-State Circuits, Vol. SC-11, No. 3. In this ROM, forty-eight (48) transistors were connected in series to form the bit lines. However, the power supply voltages were quite high, on the order of about 12-18 volts, so that the on-resistances of the series-connected transistors were relatively low. In addition, the relatively large output capacitance of each of the bit lines, once precharged, provided significant charge which could be distributed among the inter-transistor nodes during address resolution without affecting the output state.
In contrast, the series ROM described in U.S. Pat. No. 4,142,176 is designed to be operated from a single 5 volt power supply. However, the number of transistors which could be connected in series to form a word line was very limited, being on the order of seven (7), due to the cumulative voltage drops of the series-connected transistors. Adding additional transistors in series would significantly increase the time to pull the bit line sufficiently close to ground to affect the output state. To compensate for the limited column size, a group selection technique was proposed.